The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a chemical mechanical polishing (to be abbreviated as CMP hereinafter) method, a polisher used in CMP, and a method of manufacturing a semiconductor device, which employs the CMP method.
With reference to FIGS. 1A to 1E, the smoothing process which employs a conventional CMP method, in a semiconductor device manufacturing method, will now be described. Each of FIGS. 1A to 1E is a cross sectional view illustrating a stage in a smoothing process which employs the conventional CMP method.
Before carrying out the smoothing process employing the conventional CMP method, as can be seen in FIG. 1A, a silicon oxide film (SiO.sub.2 film) or a silicon nitride film (Si.sub.3 N.sub.4 film), which serves as a polishing stopper film 2, is formed on a silicon substrate 1. Then, photoresist is applied on the stopper film 2 to form a photoresist layer 3. Windows 4 having a predetermined pattern are made in the photoresist layer 3.
Next, as can be seen in FIG. 1B, the stopper film 2 and the silicon substrate 1 are etched with use of the photoresist layer 3 as a mask, so as to make a groove 5 in the silicon substrate 1. The photoresist layer 3 is removed after making the groove 5.
Further, as can be seen in FIG. 1C, the surface of the silicon substrate 1 which is exposed as the groove 5 was made, is oxidized to form a silicon oxide film (SiO.sub.2 film) 6. Then, silicon is deposited on the silicon oxide film 6 to form a silicon film 7 having a thickness larger than the depth of the groove 5. Thus, the groove 5 is filled and covered with the silicon film 7. The configuration of the surface of the silicon film 7 reflects the irregularity (projections and recesses) of the surface of the silicon substrate 1.
Next, as can be seen in FIG. 1D, the irregularity of the surface of the silicon film 7 is smoothed by the CMP method. More specifically, while supplying a polisher 16 on a polishing cloth 12 provided on a turn table 11 of a CMP device, the surface of the turn table 11 is pressed on the polishing cloth. As the turn table 11 and the substrate 1 are rotated while maintaining the above state, the projections of the silicon film 7 are polished by the polishing cloth 12 and the polisher 16, and gradually smoothed. The polisher 16 is a basic solution such as organic amine, which contains polishing particles of silica or the like. The polishing is stopped when the stopper film 2 is exposed.
The smoothing step employing the conventional CMP method is carried out in the above-described manner. The shape of the substrate 1 after the completion of the smoothing is shown in FIG. 1E.
As can be seen in FIG. 1E, with the conventional CMP method, the surface of the silicon film 7 is polished to a level lower than the level of the surface of the stopper film 2, and therefore a depression 9 is made in the surface of the silicon film 7. This phenomenon is called "dishing", which may cause the following problem.
That is, for example, in the case where an element separation region is formed by the CMP method, an undesired film remain in the depression 9 in some cases. Especially, if an electro-conductive film remains in the depression 9, wires are shortcircuited by the remaining conductive film. As a result, the yield of the production is decreased. FIGS. 2A to 2C show an example of a shortcircuit occurred between wires. FIG. 2A is a plan view of the shortcircuit between wires, FIG. 2B is a cross sectional view taken along the line 2B--2B in FIG. 2A, and FIG. 2C is a cross sectional view taken along the line 2C--2C in FIG. 2A.
As can be seen in FIGS. 2A to 2C, an element separation region 40 is embedded in the silicon substrate 1 by the CMP method. A depression 9 is made in the surface of the element separation region 40, and a conductive film 41 remains in the depression 9. As a result, wires 42-1 and 42-2 which are in contact with the element separation region 40 and arranged to be a predetermined distance away from each other, are electrically connected to each other via the conductive film 41. In other words, a electrical shortcircuit takes place between the wires 42-1 and 42-2.
Further, for example, in the case where the internal wiring of a semiconductor integrated circuit device is formed by the CMP method, the depression 9 causes decrease in the cross sectional area of the internal wiring, thus increasing the electrical resistance of the internal wiring. This phenomenon is called "attenuation of wiring". FIG. 3 shows an example of the "attenuation of wiring".
FIG. 3 is a cross sectional view of a semiconductor integrated circuit device. In this figure, an interlayer insulating film 43 is formed on the silicon substrate 1. In the interlayer insulating film 43, internal wires 44-1 to 44-4 are formed as they are embedded, by the CMP method. A depression is made in each of the internal wires 44-1 to 44-4. Therefore, the cross sectional area of each of the internal wires 44-1 to 44-4 is rendered smaller than the original cross sectional area shown by a broken line in the figure, by a portion corresponding to the depression 9. As a result, the resistance of each of the internal wires 44-1 to 44-4 is increased.
As described above, the "dishing" causes a shortcircuit between wires, and an increase in resistance of internal wires, and therefore the production yield of semiconductor device is lowered.